View GD16588-EB_6773051.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description gd16584 and gd16588 are receiver chips for use in stm-64/192 and optical transport networking (otn) systems. the component is available in two ver - sions: gd16584 for 9.5328 gbit/s. gd16588 for 10.66 gbit/s for otn or forward error correction (fec). except the different operating bit rates the two versions are functional identical. the receiver is a clock and data reco - very ic with: a low noise vco a bang-bang phase detector a 1:16 de-multiplexer a lock detect a phase and frequency detector. clock and data are regenerated by using a phase locked loop (pll) with an ex- ternal passive loop filter. the vco frequency is controlled by one of the two phase detectors in order to ensure capture and lock to the line data rate. the lock detector circuit monitors the vco frequency and determines when the vco is within the lock range. when the frequency deviates more than 500 ppm from the reference clock, it automatically switches the phase and fre - quency detector into the pll loop. in the auto lock mode the locking range is selectable between 500 or 2000 ppm. when the vco frequency is within the lock range, the bang-bang phase detec - tor takes over. it controls the phase of the vco until the sampling point of data is in the middle of the bit period, where the eye opening is largest. a 40 mv decision threshold control (dtc) is pro - vided at the 10 gbit/s input. the 10 gbit/s input data is sampled and de-multiplexed by the 1:16 demux. the parallel output interface is synchronised with the 622 mhz output clock. the clock and data outputs are lvds compatible. the device operates from a dual -5.2 v and +3.3 v power supply. the power dis- sipation is 3.3 w, typical. the device is manufactured in a silicon bipolar process and packaged in an 132 ball 13 13 mm ceramic/plastic ball grid array (bga). an intel company data sheet rev.: 12 preliminary features complete clock and data recovery ic with auto acquisition. 1:16 demux with differential 622 mbit/s data outputs 622 mhz clock output. lvds compatible clock and data outputs. oif99.102.5 compliant timing. 155 or 622 mhz reference clock. input decision threshold control (dtc): 40 mv. low noise vco with 5 % tuning range. dual supply operation: -5.2 v and +3.3 v. power dissipation: 3.3 w (typ). silicon bipolar technology. available in three package versions: ? eb: 132 ball (16 mill) ceramic bga1313mm ? ef: 132 ball (20 mill) ceramic bga1313mm ? fb: 132 ball (20 mill) plastic bga1313mm available in two versions: ? gd16584 for 10 gbit/s ? gd16588 for 10.66 gbit/s applications telecommunication systems: ? sdh stm-64 ? sonet oc-192. ? optical transport networking (otn) ? fec applications fibre optic test equipment. submarine systems. 10 gbit/s receiver, cdr and demux gd16584/gd16588 (fec) decision threshold control timing control vctl di din dtc dtcn refck refckn sel3 sel1 sel2 tck reset vcc vdd vdda vddo vee veea ckout do0 do15 parallel output data (phigh) (plow) pctl lock ckoutn don0 u d don15 1/4 vco bang bang phase detector 1:16 demultiplexer phase frequency detector lock detect
functional details the application of gd16584 is as re - ceiver in sdh stm-64 and sonet oc-192 optical communication systems. it integrates: a voltage controlled oscillator (vco) a bang bang phase detector a lock detect circuit a 1:16 demux a phase and frequency detector (pfd). vco the vco is an lc-type differential oscil - lator, voltage controlled by pin vctl and with a tuning range of approximately 5 %. for gd16584, with the vctl voltage at approximately -3.5 v, the vco fre - quency is fixed at 9.953 ghz and by changing the voltage from 0 to -5.2 v the frequency is controlled from 8.9 ghz to 10.2 ghz. the modulation bandwidth of vctl is 90 mhz. pfd the pfd ensures predictable locking conditions for the device. it is used dur- ing acquisition and pulls the vco into the locking range where the bang-bang phase detector acquires lock to the in- coming bit-stream. the pfd is made with digital set/reset cells giving it a true phase and frequency characteristic. the reference clock input (refck/refckn) to the pfd is differential and selectable between 155 mhz or 622 mhz by sel3. the reference clock is a cml input with 50 internal termination resistors to 0 v. the reference clock is typically an x-tal oscillator type as shown in figure 1 . the reference clock input should be used dif - ferential for best performance. if the ref - erence clock is dc coupled the input voltage swing i s 0 v (high) and -0.4 v (low). bang-bang phase detector the bang-bang phase detector is de - signed as a true digital type producing a binary output. it samples the incoming data prior to, in the vicinity of and after any potential bit transition. when a transition has occurred, these three samples tell whether the vco clock leads or lags the data. the binary output is filtered through the (low pass) loop fil - ter, performing an integration of all poten - tial bit transitions. hence the pll is controlled by the bit transition point. loop filter a passive loop filter is used for the cmu consisting of a resistor and a capacitor driven from the pctl pin. the pctl pin outputs the phase information from the bang-bang phase detector. the phase information is very high frequency pulses (200 ps pulse width) either charging or discharging the external capacitor. the values of the external components determines the characterisctics of the pll, e.g. bandwidth and transfer func - tions. for recommended loop filter val - ues, please refer to figure 1 . the pcb lay-out of the external loop filter and the connecting lines between pctl and vctl are critical for jitter perfor - mance of the device. the external com - ponents and the artwork should be placed very close to the pins of the device. if the phigh and plow outputs are not used they must be shorted vdd (0 v), please refer to figure 1 . lock detect circuit the lock detect circuit continuously moni- tors the difference between the reference clock and the vco clock. if they differ by more than 500 ppm (or 2000 ppm), it switches the pfd into the pll, to pull it back into the locking range. the status of the lock circuit is given by output pin (lock). manual or automatic lock is se - lected by sel1. in auto lock mode, the lock range 500 or 2000 ppm is se - lected by sel2. the lock output is an open collector output, and should be ter - minated with an external resistor. the maximum termination voltage is +3.5 v. the inputs the input amplifier pin (di/din) is de - signed as a gain buffer stage with high sensitivity and internal 50 resistors ter - minated to 0 v. after retiming, the data is de-multiplexed down to 16 bit/s by demultiplexer. it is recommended to use the 10 gbit/s inputs differentially for best input sensitivity. the input voltage decision threshold is adjustable by pin dtc and dtcn when connected to a potentiometer. adjusting the resistor value of the meter controls the current into dtc and dtcn. this dc current is mirrored to the input pin (di and din) whereby the dc bias voltage at the input is adjustable by 40 mv. opti - mizing the input decision threshold im - proves the system input sensitivity by 1-2 db typical. the input impedance into dtc and dtcn is 1.5 k and when not used they should be de-coupled t o0vby100nf. the select inputs (sel1-3, reset and tck) are low speed inputs that can be connected directly to the supply rails (0 / -5.2 v). the 10 gbit/s inputs (di and din) are not esd protected and extra precau - tions are needed when handling these in - puts. (internal 50 resistors provide some esd hardness making the input low impendance.) bit order the serial data stream is demultiplexed with the first received bit on do0, the second on do1 and with last received bit in a 16 bit frame on do15. the naming is opposite to the oif99.102.5 recommen- dation. for oif interfaces the data pins should be connected as shown in the following table. note: the clock output is inverted in order to refer the data cross- ing to the rising edge of ckoutn output pin: oif: do0/don0 rxdata15_p/n (msb) do1/don1 rxdata14_p/n do2/don2 rxdata13_p/n do3/don3 rxdata12_p/n do4/don4 rxdata11_p/n do5/don5 rxdata10_p/n do6/don6 rxdata9_p/n do7/don7 rxdata8_p/n do8/don8 rxdata7_p/n do9/don9 rxdata6_p/n do10/don10 rxdata5_p/n do11/don11 rxdata4_p/n do12/don12 rxdata3_p/n do13/don13 rxdata2_p/n do14/don14 rxdata1_p/n data sheet rev.: 12 gd16584/gd16588 page 2 of 15
output pin: oif: do15/don15 rxdata0_p/n (lsb) ckout rxclk_n ckoutn rxclk_p the outputs the data and clock outputs are lvds compatible outputs with internal bias re - sistors (500 ) to vcc (+3.3 v) refer to item ? lvds compatible inter - face ? on page 6 . timing to system asic the timing between gd16584 and the system asic at 622 mbit/s is controlled by the 622 mhz output clock synchro - nized with the output data. the clock is used as the input clock to the asic, clocking the input data into 16 parallel registers. the timing relation between the clock and data is given by the ac characteristics. for a oif99.102.5 complaint timing the output clock should be inverted by using: ckoutn as the positive output clock (rxclk_p), and ckout as the negative output clock (rxclk_n) external circuit the external circuits needed to make the device work as a complete clock and data recovery with automatic acquisition are: a passive loop filter an x-tal oscillator or reference clock (155 mhz or 622 mhz) de-coupling capacitors package the device is packaged in an 132 ball ceramic/plastic bga (13 13 mm). for the package outline, please refer to the figures on page 13 and 14 . in ceramic package the following pin pairs are individually shorted inside the package and mainly used as power pins: c3/d3, c4/d4, c5/d5, c8/d8, c9/d9, c10/d10, j3/k3, j4/k4, j5/k5, j8/k8, j9/k9, and j10/k10. thermal condition the device dissipates 3.3 w from a dual voltage supply ( ? 5.2 v and +3.3 v). the power consumption from the -5.2 v sup - ply is approximately 2.9 w and 0.4 w from the +3.3 v supply. the die is mounted on a metal pad di - rectly connected to the center balls (e4-9, f4-9, g4-9, and h4-9). it is important to have a good thermal connection from the center balls of the package via the pcb to the ambient en - vironment to ensure the best thermal conditions. note: to obtain t case <70 c, the pgba requires (compared to the cbga) additional cool - ing on the case. for details, please refer to application note ? pbga - thermal data.... ? . 10.66 gbit/s application a version of the transmitter with a bit rate of 10.66 gbit/s for forward error correc- tion application is available. the part number is gd16588. the functionality and the pin-out are identically to gd16584. the center frequency of the vco (10.66 ghz) is the only difference to gd16584. data sheet rev.: 12 gd16584/gd16588 page 3 of 15
applications figure 1. application information. figure 2. de-coupling of the power supply. data sheet rev.: 12 gd16584/gd16588 page 4 of 15 330 150 33nf 500 500 -5.2v -5.2v -5.2v 100nf 43 330 -5.2v 7 1 1 0 0 8 14 xo-pecl 155/622 mhz kvg 10gbit/s cml driver 220 vdd 100nf vref + - 0v +3.3v 16 16 0v vdd -5.2v tck do0..do15 ckout don0..don15 ckoutn framer lock plow phigh vctl pctl reset sel1 sel2 sel3 di 50 msl 0v 0v -5.2v -5.2v 50 msl vdd din dtc dtcn refck refckn vee/veea vdda -5.2v vdd/vdda/vddo vcc 0v -5.2v 0v 10k gd16584/gd16588 1 pin a1 pin c2 pin d11 vdd vddo vcc vdda vee vee pins refer to the pin list; veea pins c3 and d3 vdd pins refer to pin list veea vdd pin a4 pin b2 pin k12 pin k4 pin m12 c cc c cc cccccccccc 10f 10 f 10 f c is 1000nf parallel with 100pf.
applications continued 10 gbit/s input interface figure 3. 10 gbit/s input (di/din), dc coupled figure 4. 10 gbit/s input (di/din), ac coupled data sheet rev.: 12 gd16584/gd16588 page 5 of 15 post- amplifier gd16584/gd16588 50 msl 50 220 220 50 0v -5.2v -5.2v -5.2v di din 100nf postamplifier gd16584/gd16588 0/-0.4v 0/-0.4v 50 msl 50 50 >16ma 50 0v -5.2v 0v di din
lvds compatible interface figure 5. lvds compatible output. reference clock input figure 6. reference clock input (refck/refckn), differential ac coupled. data sheet rev.: 12 gd16584/gd16588 page 6 of 15 gd16584 or gd16585 lvds input 50 msl 500 500 100 8ma +3.3v +3.3v 0v -5.2v vcc refck refckn gd16584 50 500 500 100nf 0v 0v -5.2v -5.2v -5.2v
pin list mnemonic: pin no.: pin type: description: do0, don0 do1, don1 do2, don2 do3, don3 do4, don4 do5, don5 do6, don6 do7, don7 do8, don8 do9, don9 do10, don10 do11, don11 do12, don12 do13, don13 do14, don14 do15, don15 a8, b8 a9, b9 a10, b10 a11, a12 c11, c12 d12, e12 g11, h12 j12, j11 m11, l10 m10, l9 m9, l8 l6, k6 m5, l5 l4, m3 m2, m1 k3, l2 lvds out data output, differential 622 mbit/s. demultiplexed to output with do0, do1...do15 as first received bits. note: the bit naming convention is opposite to oif99.102.5: do0 is msb. please refer to item ? bit order ? on page 2. refck, refckn a5, a6 cml in reference clock input, differential 155 mhz or 622 mhz. sel1, sel2 c5, b5 ecl in clock and data recovery setup. sel1 sel2 0 0 auto lock, 500 ppm. 0 1 auto lock, 2000 ppm. 1 0 manual phase freq. detector (pfd). 1 1 manual bang-bang phase detector. when left open, the inputs are pulled to vdd. sel3 k11 ecl in sel3 0 155 mhz reference clock. 1 622 mhz reference clock. when left open, the input is pulled to vdd. di, din h1, e1 cml in data input, differential 10 gbit/s. no esd input protection. ckout, ckoutn l12, l11 lvds out clock output, differential 622 mhz. note : the clock polarity is opposite to oif99.102.5. please refer to item ? bit order ? on page 2 and figure 1. lock c6 open collector lock detect output. when low, the divided vco frequency deviates more than 500/2000 ppm from refck/refckn, should always be terminated with a resistor to vdd. pctl b3 analogue out charge pump output. connected to an external passive loop filter. vctl b1 analogue in vco voltage control input. dtc, dtcn m6, k5 analogue in decision threshold control. (phigh, plow) a3, b4 open collector not used. always terminate to vdd. tck c1 ecl in connect to vdd. used for test purpose. when left open, the input is pulled to vdd. reset l1 ecl in connect to vee. not needed on power up, used for test purpose. vdd a1, a4, b6, c10, d1-2, d6, d10, e4-9, f1-2, f4-9, f11, g1-2, g4-9, h4-9, j1-2, j4, j7, k4, m12 pwr digital ground 0 v. vdda b2 pwr pll ground 0 v. vddo c2 pwr vco ground 0 v. for test purpose, connect to vee. vcc d11, k12 pwr +3.3 v digital supply voltage. data sheet rev.: 12 gd16584/gd16588 page 7 of 15
mnemonic: pin no.: pin type: description: vee c4, c8, d4, d7-8, j8-9, k1, k8-9 pwr -5.2 v digital supply voltage. veea c3, d3 pwr -5.2 v pll supply voltage. nc a2, a7, b7, b11-12, c7, c9, d9, f12, g12, j6, j10, k2, k7, k10, l3, l7, m4, m7-8, not connected. reserved for future use. nc d5, j3, j5 do not connect package pinout figure 7. packages eb and ef pinout. top view - seen through the package data sheet rev.: 12 gd16584/gd16588 page 8 of 15 123456789101112 xxx xxx = internally shorted in the package a b c d e f g h j k l m 123456789101112 a b c d e f g h j k l m vctl tck din di don14 nc vdda vddo nc vee don15 reset do14 (empty) = vdd (phigh) pctl veea veea nc do15 nc don13 (plow) vee vee do13 nc refck sel2 sel1 lock nc nc dtcn don12 do12 refckn nc don11 do11 dtc nc nc nc vee nc nc nc do0 don0 don10 nc do1 don1 nc vee nc vee vee vee vee vee don9 do10 do2 don2 nc nc don8 do9 do3 nc do4 vcc do6 don7 sel3 ckoutn do8 don3 nc don4 do5 don5 nc nc don6 do7 vcc ckout
figure 8. package fb pinout. top view - seen through the package data sheet rev.: 12 gd16584/gd16588 page 9 of 15 123456789101112 xxx xxx = internally shorted in the package a b c d e f g h j k l m 123456789101112 a b c d e f g h j k l m vctl tck din di don14 nc vdda vddo nc vee don15 reset do14 (empty) = vdd (phigh) pctl veea veea nc do15 nc don13 (plow) vee vee do13 nc refck sel2 sel1 lock nc nc dtcn don12 do12 refckn nc don11 do11 dtc nc nc nc vee nc nc nc do0 don0 don10 nc do1 don1 nc vee nc vee vee vee vee vee don9 do10 do2 don2 nc nc don8 do9 do3 nc do4 vcc do6 don7 sel3 ckoutn do8 don3 nc don4 do5 don5 nc nc don6 do7 vcc ckout
maximum ratings these are the limits beyond which the component may be damaged. all voltages in table are referred to vdd. all currents are defined positive out of the pin. vddis0vor gnd. symbol: characteristic: conditions: min.: typ.: max.: unit: v ee negative supply -6 0 v v cc positive supply +4 v v o lvds lvds output voltage 0 v cc +0.5 v i o lvds lvds output current note 1 -24 24 ma v i cml, ecl cml and ecl input voltage v ee +2 0.5 v i i cml cml input current note 1 -24 24 ma v o oc open collector output voltage v ee -0.5 0 v i o oc open collector output current note 1 -12 0 ma v esd static discharge voltage hbm, note 3 500 v cdm, note 4 50 v t j junction temperature note 2 -55 +125 c t s storage temperature -65 +125 c note 1: nominal supply voltages. note 2: the maximum junction temperature equals a maximum case temperature of 95 c (top side) with the device mounted on the gd90584/585 evaluation board. note 3: human body model: mil 883d 3015.7 standard. note 4: charge device model.: jesd2-c101 standard. data sheet rev.: 12 gd16584/gd16588 page 10 of 15
dc characteristics t case *=0 cto70 c. vee = -5.2 v, vcc = +3.3 v. vdd i s0vor gnd. all voltages in table are referred to vdd. all currents are defined positive out of pin. symbol: characteristic: conditions: min.: typ.: max.: unit: v ee negative supply voltage -5.46 -5.2 -4.94 v i ee negative supply current 455 550 660 ma v cc positive supply voltage 3.135 3.3 3.465 v i cc positive supply current -180 -140 ma v oh lvds lvds output voltage high note 7, v cc = 3.3 v 1.4 1.5 v v ol lvds lvds output voltage low note 7, v cc = 3.3 v 0.9 1.1 v v od lvds lvds output differential voltage note 7, v cc = 3.3 v 250 400 600 mv v ih cml cml input voltage high -0.1 0 +0.1 v v il cml cml input voltage low -1 -0.4 -0.25 v i ih cml cml input current high v ih cml ,50 input 0 ma i il cml cml input current low v il cml ,50 input 8 ma r in cml cml input resistor termination dc 40 50 60 i oh oc open collector output current high note 1, 3 -0.1 0 +0.1 ma i ol oc open collector output current low note 1, 3 -10 -8 -7 ma v ih ecl ecl input voltage high note 2, 5 -1.1 0 v v il ecl ecl input voltage low note 2, 5 v ee -1.5 v i ih ecl ecl input current high v = -1.1 v 30 a i il ecl ecl input current low v = -1.5 v 30 a vads offset adjustment by dtc/dtcn, differential note 4, 6 90 mv note 1: output externally terminated by 50 to0v. note 2: all ecl inputs can be connected directly to vdd/vee. note 3: all open collector outputs should always be terminated with a resistor. note 4: with dtc and dtcn connected to a 10k potentiometer with the mid pin grounded (0 v). note 5: -5.0 v. note 6: with open data inputs. note 7: with 100 termination resistor. *: t case measured at the center of the top. data sheet rev.: 12 gd16584/gd16588 page 11 of 15
ac characteristics t case *=0 cto70 c. vee = -5.2 v, vcc = +3.3 v. figure 9. oif99.102.5 complaint timing relation between the negative output clock (ckoutn) and output data (do0-15). symbol: characteristic: conditions: min.: typ.: max.: unit: j tol jitter tolerance f < 400 khz 4mhz package outline figure 10. package 132 ball ceramic bga (eb and ef package). all dimensions are in mm. data sheet rev.: 12 gd16584/gd16588 page 13 of 15 ef - package
figure 11. package 132 ball plastic bga (fb package). all dimensions are in mm. data sheet rev.: 12 gd16584/gd16588 page 14 of 15
device marking figure 12. device marking. top view. the black square marks location of ball a1. ordering information to order, please specify as shown below: product name: version : package type: intel order number: case temperature range: gd16584-eb 10 gbit/s 132 ball (16 mill) ceramic bga hcgd16584eb mm# 835478 0..70 c gd16584-ef 10 gbit/s 132 ball (20 mill) ceramic bga hcgd16584ef mm# 837347 0..70 c gd16584-fb 10 gbit/s 132 ball (20 mill) plastic bga rcgd16584fb mm# 836957 0..70 c GD16588-EB 10.66 gbit/s 132 ball (16 mill) ceramic bga hcgd16588eb mm# 835480 0..70 c gd16588-ef 10.66 gbit/s 132 ball (20 mill) ceramic bga hcgd16588ef mm# 837349 0..70 c gd16588-fb 10.66 gbit/s 132 ball (20 mill) plastic bga rcgd16588fb mm# 836962 0..70 c gd16584/gd16588, data sheet rev.: 12 - date: 2 november 2001 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.intel.com/ixa please check our internet web site for latest version of this data sheet. distributor: copyright ? 2001 giga aps an intel company all rights reserved an intel company gd16584- - gd16588- -

▲Up To Search▲

Price & Availability of GD16588-EB

	To Download GD16588-EB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .